Scheduling In FPGA / Board-Level Design Projects

An FPGA / Board-level project is essentially two different tasks: the design of the FPGA and the design of the board. There are different methods used to schedule these two tasks, and some work better than others. The critical milestone where these two tasks meet is at the point where the FPGA symbol must be generated for the schematic entry system. At one extreme, some companies prefer to build the board first, pre-defining the FPGA pins but leaving the FPGA design essentially blank until after the board is complete. This approach is very risky and often leads to problems with pin assignments being left out or not configured to the necessary dedicated pins on the device.

The approach that we take a Verien is to design the FPGA to the point where each individual module in the design has had basic testing - essentially the design of the FPGA is complete, but system level simulation has not been performed yet. Concurrently with the FPGA effort, the board design (schematic entry) can be completed to the point where the FPGA symbol is required. With the FPGA design complete, it is possible to automatically generate a schematic symbol from the placed and routed FPGA design. Once the FPGA symbol has been generated, schematic design continues and FPGA system-level simulation commences. We have used this method for many successful designs; designs that require little or no PCB rework.

Please contact us if you have any questions on this, or to provide feedback. Thank you!