FPGA Tips

The following pages provide a number of tips on the design of FPGAs. Most of the information is based upon Xilinx FPGAs, although much of it applies to the other FPGA families, as well. If you have any questions or comments regarding this info, please contact us at: info@verien.com.


RTL for FPGAs
This is a collection of notes on RTL coding for success. You can view the entire collection from the above link, or go directly to the following subjects:

• Use of Reset
• Resource Sharing
• Clocks
• Decoding Register Writes
• State Machines
• Project Packages
• Testbench Design
• Specifying Model Timing via Generics
• Performing Timing Checks
• Performing Protocol Checks
• Handling Large Counters

• Recommended Design Practices for High Performance
• Achieving Timing Closure

• Beware of Strobe Glitches!
• TLP Buffering
• Receiver Completion Streaming
• PCIe Error Reporting
• Completion Packets
• PCIe Byte Order
• PCIe Legacy Interrupts
• PCIe Simulation Test