Example Projects

The following are examples of products designed by Verien Design Group. In all cases, Verien provided the custom integrated circuit design services, and in some cases, Verien provided the board design services in addition to the IC design services.

The ECT DAS The ECT DAS is an Electrical Capacitance Tomography Data Acquisition System. This is a type of tomography used for industrial process monitoring to image fluid or solid flow in pipes. A section of pipe is surrounded with an array of plates, called a capacitance cell. The capacitances between all plate pairs are measured. The ECT DAS that Verien designed can drive up to 24 plates, providing 276 distinct plate pair combinations, measuring with a resolution of 1 femtofarad. The DAS dynamically balances out the standing capacitances of the cell, typically 1 picofard, and the effects of cable capacitance, typically 500 picofarads. It operates at a rate of 50 frames per second, providing real time digitization of the flow. This mixed signal design uses a Virtex-5 FPGA which interfaces to DAC's, ADC's, multiplexer banks and programmable gain amplifiers. Automatic calibration is available on command. USB and RS-232 communication ports are provided for connection to the host computer.

The SAM Atomic Physics Precision Measurement Board The SAM design is a mixed signal embedded product which utilizes a Virtex-5 XC5VFX70T with 400 MHz PowerPC processorTM and IEEE-754 double precision floating point unit coupled to the auxiliary processor interface. Two custom DDS generators (44-bit phase resolution) are used to modulate two lasers with 18 bits of precision by summing 14-bit DACs for modulation, and 20-bit DACs for offset. Two photodiode amplifiers and 14-bit ADCs acquire the data for real-time processing in the FPGA. The FPGA digital signal processing is performed in both fixed and single precision floating point hardware to support the wide dynamic range required. The photodiode input section was designed by customizing instantiated DSP48E slices in the FPGA. In addition, the design contains multiple heater and temperature sensing interfaces: one uses a PWM driving a Class-D amplifier to drive a heater cable and a lock-in amplifier to extract the temperature from an RTD using AC excitation (no DC component). The second is a Thermal Electric Cooler and thermistor interface to control the temperature of the lasers to within 1 mK. Verien worked closely with the client to define the product, and then designed the analog circuitry, FPGA, board, and provided the diagnostics running on the embedded PowerPC.

CAT Scan Processor These FPGAs provide many of the processing stages for an explosion detection system used for baggage inspection. The design was mixed VHDL and with MatlabTM / SimulinkTM blocks integrated through Xilinx System Generator for DSP tool. These two XC4VSX55 devices run at a data rate of 133 MHz and provide in excess of 1.5 GBytes/sec of DDR2 bandwidth. Development in Matlab / Simulink provided for a rich DSP environment. Simulink blocks from the Xilinx blockset were integrated into a top-level VHDL, and then the Simulink and VHDL simulation data was regression tested.

Cardiac Ultrasound Processor This FPGA performed the real-time digital signal processing of cardiac ultrasound images. Implemented in a low-cost Spartan3TM device (XC3S1500), it provides 17 stages of 1D and 2D processing at 160 MHz (40 MHz sample rate), a scatter/gather DMA controller, and PCI bursting target and initiator interfaces. The client came to Verien with the DSP algorithms implemented in C; Verien redesigned these in VHDL and regression tested the output data from the C version against the FPGA simulation. The Xilinx CoregenTM tool was used to implement 31 and 63 tap symmetric FIR filters and with decimation and other processing stages designed from scratch. The Xilinx PlanAheadTM tool was used to achieve the 160 MHz rate.

Dual Gigabit Communications Link This client needed a large packet data mover for an industrial imaging application. The result is a dual 1.3 Gb/sec optical card that achieves a measured 220 Mbytes/sec over 64-bit, 66 MHz PCI. The PCI interface is implemented with a PLXTM PCI-9656 and all header encapsulation and processing is performed in a Xilinx XC2V1000. Out of band mailbox transfers are provided as a means of communication between the boxes.

The Real Time Data Interface The RDI is a custom PCI card used for real time distributed motion control systems. This PCI card provides four 500 Mbit/sec links for reliable packet communications, eight linked-list DMA engines which allow real-time scheduled transfers, and nanosecond-class box-to-box synchronization for distributed real-time control operations. All packet processing is implemented in the Xilinx Spartan3TM FPGA including encapsulation into small packets (for known real-time latency), 8B/10B encoding, CRC generation and checking. Transfers can be either reliable (acknowledged and retried in hardware) or UDP-style with a sequence number provided at the destination. All logic was implemented in the FPGA including the PCI target and bursting initiator, with a Cypress Hotlink IITM transceiver used for the physical interface (FPGA LVDS interface for clock and servo cycle synchronization). Verien designed both the FPGA, as well as the PCI card.

The Servo Interface Board The SIB is an endpoint for an RDI-based real time motion control system (see the RDI description above). This card provides one 500 Mbit/sec real-time link for communication to the RDI, four A/Ds for analog (sine/cosine) optical encoder interfaces, LVDS trigger input and output, six channels of differential analog input (A/D), eight DAC output channels, I2C EEPROM, power supplies, and a mayday timer. A Xilinx Spartan3ETM FPGA is used for the real-time communications link and all converter interfaces which run in clock and servo cycle synchronization with the RDI and other boards in the system. Verien provided turnkey design services for this product.

Controller Area Network PCI Express Card This embedded card provides control for the Boston Dynamics Petman robot, used for testing chemical protection clothing. It is a COM Express carrier card measuring 95 x 125 mm with active components on both sides. It mates with an off-the-shelf COM Express processor card and communicates via PCI Express, providing the physical interface for all of the I/O from the computer module: VGA, 3 USB ports, Gigabit Ethernet, and IDE. The FPGA (Virtex-5) provides 10 Controller Area Network interfaces which communicate to all of the robot axes, as well as two serial ports, an NVSRAM interface, and an SDLC interface to an Inertial Measurement Unit (IMU), a watchdog timer, and other I/O. A custom DMA engine is used to DMA the CAN data to host memory across the PCI Express interface. The IMU interface is implemented through ring buffers internal to the FPGA. The Verien provided turnkey design services for this product delivering working prototypes.

Controller Area Network PCI Card This embedded card provides control for a small robot for a specialized military application. It is a 2.5inch x 4.7inch card on which a 500 MHz computer module is mounted. The card provides the physical interface for all of the I/O from the computer module: VGA, serial ports, 3 USB ports, Ethernet, IDE, and I2C. The card also contains an Xilinx Spartan3E FPGA which interfaces from the PCI bus to four Controller Area Network buses. The FPGA contains four separate CAN cores which operate up to 4 Mbps with four acceptance masks/filters for each of the interfaces. Also provided in the FPGA is the ability to generate autonomous CAN cycles based upon a programmable timer. In addition, four switching supplies were required to meet the target efficiency and high current requirements (9v - 50v input with 7A output). Verien provided turnkey design services for this product delivering working prototypes.

MADI (AES10) Audio Bridge The product is a digital audio bridge which is compliant to the AES10 (MADI) digital audio specification - essentially a multi-channel version of AES3 (S/PDIF or AES/EBU). This board implements a bidirectional digital audio connection between multiple TDM streams and MADI over copper. The MADI interface provides up to 64 channels in each direction at a fixed 125 Mbit/sec rate. All formatting including AES3 status block, 4B/5B and NRZI encoding is performed in an Actel ProASIC3TM FPGA. Internal loopback testing was added to the FPGA allowing the entire board to be tested with nothing more than a power supply and a cable. The physical interface (also designed by Verien) was galvanically isolated to prevent ground loops for this remote application.

Embedded Binocular Vision System Based upon the TI TMS320DM642 DSP, this low cost embedded system provides image acquisition and processing from two CMOS sensors, video display, FLASH, SDRAM, I2C, real time clock, and Ethernet. The programmable logic provides most of the glue for the system: sync generation, an optical encoder interface, a PWM heater controller, and other necessary functions.

Four Port PCI Frame Grabber Daughtercard This frame grabber daughtercard provides two image acquisition channels with four camera ports (through 2:1 analog muxes) at 40 MSPS. It supports progressive scan cameras and flexible image acquisition rates, along with a pass-through display channel. This product interfaced to this clients proprietary bus as a plug-in daughtercard.

The Anywhere Pixel Compositor The Anywhere Pixel Compositor is a research project for the University of Kentucky Graphics Vision Technology Laboratory. The product allows any of four video inputs to be acquired and blended with bilinear interpolation, and output to any of four video outputs. Verien provided a redesign of the FPGA to support bilinear interpolation and implemented a custom image caching scheme to achieve the required bandwidth from DDR memory for real time acquisition and display. More about the product can be learned at the University of Kentucky website here.

Wafer Inspection System This system is used for the inspection of wafers during etch and essentially uses each pixel of a CCD as an interferometer. The client needed to have a camera with thermally controlled CCD array in a very small package, and desired to connect up to four of these cameras to a single frame grabber with image processing performed on the live data. The result was the development of an actively cooled camera (using Peltier coolers) approximately 1" x 2" x 3" in size and which contained the A/D and several DACs, all CCD timing generation and control, as well as a differential interface back to the frame grabber. The frame grabber captured four live video streams, performed image processing on the streams, and then transferred the data to host memory across the PCI bus.

Wafer Repair System This is a large industrial machine used for the repair of semiconductor wafers. Specifically, it is used to disable faulty rows and columns and enable redundant rows and columns in memory wafers for improved yield. The digital servo subsystem consists of three boards and three FPGAs. The main FPGA contains a command execution unit with custom instruction set, laser fire command FIFO, VMEbus interface, and memory interface. This board communicates with two other boards which provide interfaces to a wide variety of sensors (optical encoders and LVDTs) and converters (A/D and D/A). The entire system is synchronous to a 40 MHz clock which is used to generate the fundamental servo cycle.

Programmable MEMS Test System This system consists of two FPGA designs which implement a programmable MEMS tester. One FPGA is for programmable stimulus generation and the second is for the VXI bus interface to the host. The stimulus generation chip contains a custom execution unit with proprietary instruction set geared toward the application. The execution unit controls various DUT interfaces such as a Serial Peripheral Interface (SPI) port, a Manchester encoded asynchronous interface port, an event counter, and memory interface. Four of the stimulus chips were interfaced to the VXI bus through the VXI interface FPGA.

RISC Microprocessor Chipset This is a two ASIC chipset used to interface a MIPSTM RISC microprocessor to various I/O ports and memories. The chipset set provides two-way interleaved memory controller, programmable I/O controllers, keyboard and mouse interfaces, audio interface, video sync generator, and more. The chipset shipped over 100,000 units in first pass silicon.