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PCI Express Tutorial

PCI Express Tutorial

PCI Express Topology

PCI Express is a serial point to point link that operates at 2.5 Gbits/sec (Gen 1) and higher rates in each direction and which is meant to replace the legacy parallel PCI bus. PCI Express (PCIe) is designed to provide software compatibility with older PCI systems, however the hardware is completely different. Since PCIe is point to point, there is no arbitration for resources on the link. Each pair of links (both directions) is referred to as a "lane", and multiple lanes can be aggregated to form a single higher bandwidth connection. The following sections describe some of the details of the PCIe interface.

As can be seen in the figure below, a PCI Express fabric consists of three types of devices: the root complex, switches, and endpoints. The root complex is generally associated with the processor and is responsible for configuring the fabric at power-up. Since PCIe connections are point to point, switches are used to expand the fabric. PCIe endpoints are the I/O devices in the fabric - the sources of, and destinations for the data.

PCI Express Fabric

PCI Express Layers

PCIe is implemented in three of the OSI model layers: the transaction layer, the data link layer, and the physical layer. The following figure displays the layers as connected between two PCIe devices.

PCI Express Layers

As can be seen in the figure, the user logic interfaces to the transaction layer. The user forms Transaction Layer Packets, or TLPs which contain a header, data payload, and optionally an end-to-end CRC, ECRC. The ECRC, if used, is generated by the user logic at the transmitter and checked by the user logic at the receiver. The data link layer is responsible for link management including error detection. In this layer, a CRC (called the Link CRC or LCRC) is appended and a sequence number is prepended to the Transaction Layer Packet. When a packet is transmitted from the data link layer, the receiver sends back an ACK (success) or NACK (failure) to the transmitter which will retransmit in the case of an error. These ACKs and NACKs are sent via special packets which originate from the data link layer called Data Link Layer Packets, or DLLPs. The physical layer consists of two differential pairs with 8B/10B encoded data allowing for a DC balance on the transmission media and for clock recovery at the destination. Framing information is added to the data link layer packet, and this is encoded and driven onto the link. The following diagram displays the encapsulation of packets in PCIe:

PCI Express Transaction Layer Packet

The transaction layer supports the notion of Virtual Channels and Traffic Classes which can be used for real-time isochronous and prioritized data transport. The maximum data payload (MDP) in a PCIe system is a system-wide user defined parameter. The desired MDP is requested in a PCIe configuration register which is read by the root complex. After polling all of the MDP values in the system, the lowest value is written to a separate configuration register on each side of the link. Legal values of the MDP are 128 bytes through 4096 bytes in powers of 2. A transmitter must not send a packet which exceeds the programmed MDP.

PCI Express Transactions

PCIe provides four types of transactions that originate at the transaction layer: memory, I/O, configuration, and message. In general, memory transactions are the basic method of transferring data. I/O transactions are provided for backward compatibility with PCI (which provided them for backward compatibility with ISA) and are not recommended for future use. Configuration transactions are similar to those of the same name in the PCI bus and are used by the root complex to configure the system upon power-up. Message transactions are new and are used to send interrupts and error conditions, as well as other information through the fabric. Transactions can be further classified as posted, non-posted, and completion. A memory write operation is an example of a posted transaction since it does not require a response from the destination. A memory read request is a non-posted transaction that will later cause a completion transaction with the read data. The completion transaction is initiated by the destination when the read data is available. Both I/O read and I/O write are non-posted transactions, as are configuration read and write. Message transactions are of type posted.

Flow Control

PCIe implements a point to point (not end to end) credit policy for managing buffers. The data link layer sends Data Link Layer Packets which indicate the amount of receiver buffer space available in units of credits. The transmitter must ensure that the buffer space is not exceeded prior to commencing a transmission.

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